Semiconductor integrated circuits are designed and fabricated by first preparing a schematic diagram or hardware description language (HDL) specification of a logical circuit in which functional elements are interconnected to perform a particular logical function. The schematic diagram or HDL specification is then synthesized into cells of a specific cell library. Each cell corresponds to a logical function unit, which is implemented by one or more transistors that are optimized for the cell. A series of computer-added design tools generate a netlist of the selected cells and the interconnections between the cells. The netlist is used by floor planner or placement tool to place instances of the selected cells at particular locations in a layout pattern. A routing tool routes the interconnections between the cells along predetermined routing layers. Once the selected cells have been placed and routed, the netlist, the cell layout definitions, the placement data and the routing data together form an integrated circuit layout definition, which is used to fabricate the integrated circuit.
An integrated circuit is fabricated by depositing layers on a substrate known as a wafer. The lowest, “base” layers include the active areas of the transistors, including the diffusion regions and the gate oxide areas, and the desired patterns of the polysilicon gate electrodes. The base layers also include other base elements, such as power and ground voltage supply rails. One or more metal layers are deposited on top of the base layers and patterned to form conductive segments, which interconnect the various elements in the base layers. Electrical contacts or vias may be formed to electrically connect a conductive segment on one of the metal layers with a conductive segment on another metal layer or an element on a base layer.
A gate array type integrated circuit has a predefined base layer layout pattern in which arrays of functionally uncommitted transistors, logic gates and other active devices and features are placed at predefined locations. The base layers can be fabricated on a substrate according to the base layer layout pattern before the overall function of the circuit has been defined. These base layers are provided by the semiconductor manufacturer and are non-programmable or configurable by the design customer.
The design customer receives a cell library and the base layer layout pattern (know as a master slice) from the semiconductor manufacturer and creates a design layout pattern for selectively “metalizing” higher metal layers that interconnect the base layer elements to implement a specified function. Once the design layout pattern is complete, the higher metal layers can be fabricated on top of the base layers to complete the integrated circuit.
One of the additional elements that is often fabricated within the base layers is an array of power supply decoupling capacitors. As the switching speeds of integrated circuits continue to increase, decoupling capacitors are being embedded in integrated circuit designs in order to stabilize the bias voltage levels throughout the integrated circuit. In gate arrays, decoupling capacitors have been placed at regular intervals in the base layer layout pattern. These decoupling capacitors can be formed as parallel plate capacitors, with one plate being formed by the diffusion region of one or more base cell locations and the other plate being formed by polysilicon, which overlaps the diffusion region. The diffusion region is electrically coupled to one power supply rail and the polysilicon layer is coupled to the other power supply rail.
Although decoupling capacitors improve the stability of voltage supply levels on an integrated circuit, design rules that govern the placement and layout of the various elements of the integrated circuit can create inefficiencies when dealing with the decoupling capacitors. For example if each decoupling capacitor instance occupies a small number of base cell locations, edge set back requirements of the base cell locations may limit the capacitance per unit area of each decoupling capacitor. However if each decoupling capacitor instance occupies a large number of base cell locations, backend placement tools may require the boundaries of macro cells that overlap one or more capacitor cells to “snap” or enlarge to the next nearest capacitor cell boundary. This increases the area consumed by the macro cell.
Another problem with the use of decoupling capacitors is the extra processing resources and database space required by the backend tools to manage the details associated with the decoupling capacitors. The existence of decoupling capacitors increases the amount of data that must be handled by backend tools. Cell placement and routing tools must take into account the presence and boundaries of the decoupling capacitor cells when placing logic gates within the layout pattern and when routing their interconnections. This increases the resource requirements in order to layout an integrated circuit design.
Improved methods and apparatus are desired for handling decoupling capacitors in integrated circuit layout designs.